Transfer Error Interrupt Enable Register (Lteir) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Local Bus Controller
Bits Name
13–29 — Reserved
30 UCCD UPM Run pattern command completion checking disable.
0 UPM Run pattern command completion checking is enabled.
1 UPM Run pattern command completion checking is disabled.
31 CCD FCM command completion checking disable.
0 Command completion checking is enabled.
1 Command completion checking is disabled.

10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR)

The transfer error interrupt enable register (LTEIR), shown in
error/event reporting through the eLBC internal interrupt mechanism. Software should clear pending
errors/events in LTESR before enabling interrupts. After an interrupt has occurred, clearing relevant
LTESR error/event bits negates the interrupt.
Offset 0x0B8
0 1 2
R
BMI FCTI PARI
W
Reset
16
R
W
Reset
Table 10-18 describes LTEIR fields.
Bits Name
0 BMI Bus monitor error interrupt enable.
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
1 FCTI FCM command time-out interrupt enable.
0 FCM command time-out error reporting is disabled.
1 FCM command time-out error reporting is enabled.
2 PARI ECC error interrupt enable.
0 ECC error reporting is disabled.
1 ECC error reporting is enabled.
3–4 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-28
Table 10-17. LTEDR Field Descriptions (continued)
3 4 5
—
WPI
Figure 10-15. Transfer Error Interrupt Enable Register (LTEIR)
Table 10-18. LTEIR Field Descriptions
Description
Figure
6 7 8 9
— WARA RAWA
All zeros
—
All zeros
Description
10-15, is used to send or block
Access: Read/Write
10 11 12 13
— CSI
29
Freescale Semiconductor
15
—
30 31
UCCI CCI