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Table 3-2. MPC8313E Signal Reference by Signal Name (continued)
Name
USBDR_PWRFAULT
USB VBus fault
USBDR_STP
USB stop
USBDR_
USB data bus 5–7
TXDRXD[5:7]
USBDR_TXDRXD0
USB data bus 0
USBDR_TXDRXD1
USB data bus 1
USBDR_TXDRXD2
USB data bus 2
USBDR_TXDRXD3
USB data bus 3
USBDR_TXDRXD4
USB data bus 4
XCOREVDD[0:2]
SerDes transceiver
core supply
XCOREVSS[0:2]
SerDes transceiver
core ground
XPADVDD[0:1]
SerDes transceiver
pad supply
XPADVSS[0:1]
SerDes transceiver
pad ground
1
See H/W specification for resistor values.
2
See
Table 3-3
for proper connection to power.
3
The LB_POR_CFG_BOOT_ECC_DIS function will be selected on the TSEC_MDC pin whenever HRESET is asserted; the pin
will act as TSEC_MDC at all other times. The reset block will sample this signal on PORESET negation only; the sampled value
is then passed to the eLBC controller to enable/disable ECC checking during boot time.
4
Must be connected to a 10K ±1% precision resistor if using the integrated USB PHY through the UTMI.
3.2
Configuration Signals Sampled at Reset
The signals that serve alternate functions as configuration input signals during system reset are
summarized in
Table
Chapter 4, "Reset, Clocking, and Initialization."
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Functional
Description
Block
USB
USB
USB
USB
USB
USB
USB
USB
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
3-3. The detailed interpretation of their voltage levels during reset is described in
Table 3-3. Reset Configuration Signals
Functional
Functional Signal Name
Interface
eTSEC2
TSEC2_TXD[3:0]
No. of
Table/
I/O
Signals
Page
1
I/O
16-1/16-3
1
O
16-2/16-4
3
I/O
16-2/16-4
1
I/O
16-2/16-4
1
I/O
16-2/16-4
1
I/O
16-2/16-4
1
I/O
16-2/16-4
1
I/O
16-2/16-4
2
3
PWR
15-2/15-8
3
GND
15-2/15-8
2
2
PWR
15-2/15-8
2
GND
15-2/15-8
Reset Configuration Name
CFG_RESET_SOURCE[0:3]
Signal Descriptions
Alternate
Table/
Function(s)
Page
GTM1_TGATE1/
5-27/5-21,
GTM2_TGATE2/
10-2/10-5
LSRCID1
TSEC1_TXD[0]/
15-2/15-8
TSEC_1588_PP3
TSEC1_RXD[3:1]
15-2/15-8
TSEC1_COL
15-2/15-8
TSEC1_CRS
15-2/15-8
TSEC1_GTX_CLK
15-2/15-8
TSEC1_RX_CLK
15-2/15-8
TSEC1_RX_DV
15-2/15-8
—
—
—
—
—
—
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3-29
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