Freescale Semiconductor MPC8313E Family Reference Manual page 508

Enhanced Local Bus Controller
When TRLX and CSNT are set in a write access, the LWE[0:1] strobe signals are negated one clock earlier
than in the normal case, as shown in
one clock earlier.
LCLK
LAD
LALE
A
TA
LCS n
LBCTL
LWE n
LOE
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4, 8)
LCLK
LAD
Address
LALE
A
TA
LCS n
LBCTL
LWE n
LOE
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-54
Figure 10-39
Address Write Data
Latched Address
ACS = 10
Figure 10-39. GPCM Relaxed Timing Write
SCY = 1, TRLX = 1
Figure 10-40. GPCM Relaxed Timing Write
10-40. If ACS ≠ 00, LCSn is also negated
and Figure
CSNT = 1
Write Data
Latched Address
CSNT = 1
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