Freescale Semiconductor MPC8313E Family Reference Manual page 412

DDR Memory Controller
Bits Name
20–23 ODT_PD_EXIT ODT powerdown exit timing (t
24–27 —
28–31 MRS_CYC
9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
DDR SDRAM timing configuration register 1, shown in
between various SDRAM control commands.
Offset 0x108
0 1 3 4
R
— PRETOACT ACTTOPRE
W
Reset
Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
Table 9-10 describes TIMING_CFG_1 fields.
Bits Name
0 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-14
Table 9-9. TIMING_CFG_0 Field Descriptions (continued)
before ODT may be asserted.
0000 0 clock
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved
Mode register set cycle time (t
Register Set command until any other command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
7 8 9 11 12
— ACTTORW
Table 9-10. TIMING_CFG_1 Field Descriptions
Description
). Specifies how many clocks must pass after exiting powerdown
AXPD
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
). Specifies the number of cycles that must pass after a Mode
MRD
1000–1111Reserved
Figure 9-6, sets the number of clock cycles
15 16 19 20 21
CASLAT REFREC — WRREC — ACTTOACT — WRTORD
All zeros
Description
Access: Read/Write
23 24 25 27 28 29
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