Mpc8313E Architecture Overview; Power Architecture Core - Freescale Semiconductor MPC8313E Family Reference Manual

— Supports wake-up from Ethernet Magic Packet, USB, GPIO, PCI (PME input as host), timer
and external interrupts
— Supports MPC8349E backward-compatibility mode
• Parallel I/O
— General-purpose I/O (GPIO)
– 32 parallel I/O pins multiplexed on various chip interfaces
– One dedicated GPIOs
— Open drain capability
— Interrupt capability
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Two general-purpose timers
• IEEE Std. 1149.1™ compliant JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
1.2

MPC8313E Architecture Overview

The following sections describe the major functional units of this device.
1.2.1

Power Architecture Core

The device contains the e300c3 Power Architecture processor core, which is an enhanced version of the
MPC603e core (used in previous generations of PowerQUICC II processors). Enhancements include
integrated parity checking, dual integer units, and other performance-enhancing features. The e300 core is
upward software-compatible with existing MPC603e core-based products.
For detailed information regarding the processor core refer to the following:
• The e300 Power Architecture™ Core Family Reference Manual (chapters describing the
programming model, cache model, memory management model, exception model, and instruction
timing) (Document No. E300CORERM)
• The Programming Environments Manual for 32-Bit Implementations of the PowerPC™
Architecture (Document No. MPCFPE32B)
The e300 core is a low-power implementation of the family of microprocessors that implements Power
Architecture technology. The core implements the 32-bit portion of the architecture, which provides 32-bit
effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
The core is a superscalar processor that can issue three instructions (two plus a branch) and completes and
retires as many as two instructions per clock cycle. Instructions can execute out of order for increased
performance; however, the core makes completion appear sequential.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Overview
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