Freescale Semiconductor MPC8313E Family Reference Manual page 413

Bits Name
1–3 PRETOACT Precharge-to-activate interval (t
until an activate or refresh command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
4–7 ACTTOPRE Activate to precharge interval (t
until a precharge command is allowed.
0000 16 clocks
0001 17 clocks
0010 18 clocks
0011 19 clocks
0100 4 clocks
8 — Reserved
9–11 ACTTORW Activate to read/write interval for SDRAM (t
command until a read or write command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
12–15 CASLAT MCAS latency from READ command. Number of clock cycles between registration of a READ command
by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge
n
and the latency is
must be programmed at initialization as described in
2 (DDR_SDRAM_CFG_2).")
0000 Reserved
0001 1 clock
0010 1.5 clocks
0011 2 clocks
0100 2.5 clocks
0101 3 clocks
0110 3.5 clocks
0111 4 clocks
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
). Determines the number of clock cycles from a precharge command
RP
RAS
0101 5 clocks
0110 6 clocks
0111 7 clocks
...
1111 15 clocks
m
clocks, data is available nominally coincident with clock edge
1000 4.5 clocks
1001 5 clocks
1010 5.5 clocks
1011 6 clocks
1100 6.5 clocks
1101 7 clocks
1110 7.5 clocks
1111 8 clocks
Description
). Determines the number of clock cycles from an activate command
). Controls the number of clock cycles from an activate
RCD
Section 9.4.1.8, "DDR SDRAM Control Configuration
DDR Memory Controller
n m
+ . This value
9-15