Etsec Receive Control And Status Registers; Receive Control Register (Rctrl) - Freescale Semiconductor MPC8313E Family Reference Manual

15.5.3.3

eTSEC Receive Control and Status Registers

This section describes the control and status registers that are used specifically for receiving Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.3.1

Receive Control Register (RCTRL)

The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must
be written only after a system reset (at initialization) or after a graceful receive stop has completed.
Figure 15-23 describes the RCTRL register.
Offset eTSEC1:0x2_4300; eTSEC2:0x2_5300
0
R
W
Reset
16 17 18
R
LF
— VLEX FILREN FSQEN GHTX IPCSEN TUCSEN
C
W
Reset
Table 15-28 describes the fields of the RCTRL register.
Bits Name
0–6 — Reserved
7 TS Time stamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less
than 8. Must be set to zero if TMR_CTRL[TE]=0.
8–10 — Reserved
11–15 PAL Packet alignment padding length. If not zero, PAL (1–31) bytes of zero padding are inserted before the
start of each received frame, but following the RxFCB if TOE is enabled. For Ethernet where optional
preamble extraction is enabled, the padding appears before the preamble, otherwise the padding
precedes the layer 2 header. The value of PAL can be set so that the start of the IP header in the receive
data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure
such alignment of the IP header.
Note that the minimum zero padding value for this field should be PAL–8 if the TS field is set and 0 when
PAL is < 8.
16 — Reserved
Lossless flow control. When set, the eTSEC determines the number of free BDs (through RQPARM n [LEN]
17 LFC
and RBTPTR n ) in each active ring. Should the free BD count in an active ring drop below its setting for
RQPARM n [FBTHR], the eTSEC asserts link layer flow control.
For full-duplex Ethernet connections, the eTSEC emits a pause frame as if TCTRL[TFC_PAUSE] was set.
For FIFO packet interface connections, the RFC signal is asserted.
0 Disabled. This is the default
1 Enabled, calculate the free BDs in each active ring and assert link layer flow control if required.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
—
19 20 21
Figure 15-23. RCTRL Register Definition
Table 15-28. RCTRL Field Descriptions
7 8
TS —
All zeros
22 23 24 25
PRSDEP
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
10 11
PAL
26 27 28
— BC_REJ PROM RSF EMEN —
15
29 30 31
15-49