Freescale Semiconductor MPC8313E Family Reference Manual page 535

LCRR[CLKDIV] = 4 or 8, the CSTn and BSTn bits determine the state of UPM signals LCSn and
LBS[0:1] at each quarter phase of the bus clock. When LCRR[CLKDIV] = 2, CST2 and CST4 are ignored
and the external has the values defined by CST1 and CST3 but extended to half the clock cycle in duration.
The same interpretation occurs for the BSTn bits when LCRR[CLKDIV] = 2.
0 1 2
R
CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4
W
Reset
16 17 18
R
G4T1/
G3T1 G3T3
DLT3
W
Reset
Table 10-40 contains descriptions of the RAM word fields.
Bits Name
0 CST1 Chip select timing 1. Defines the state (0 or 1) of LCS n during bus clock quarter phase 1 if
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 1 if
LCRR[CLKDIV] = 2.
Chip select timing 2. Defines the state (0 or 1) of LCS n during bus clock quarter phase 2 if
1 CST2
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
Chip select timing 3. Defines the state (0 or 1) of LCS n during bus clock quarter phase 3 if
2 CST3
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 2 if
LCRR[CLKDIV] = 2.
3 CST4 Chip select timing 4. Defines the state (0 or 1) of LCS n during bus clock quarter phase 4 if
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
4 BST1 Byte select timing 1. Defines the state (0 or 1) of LBS during bus clock quarter phase 1 (LCRR[CLKDIV]
= 4 or 8) or bus clock half phase 1 (LCRR[CLKDIV] = 2), in conjunction with BR n [PS] and LA[24:25].
5 BST2 Byte select timing 2. Defines the state (0 or 1) of LBS during bus clock quarter phase 2 (LCRR[CLKDIV]
= 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when LCRR[CLKDIV] = 2.
6 BST3 Byte select timing 3. Defines the state (0 or 1) of LBS during bus clock quarter phase 3 (LCRR[CLKDIV]
= 4 or 8) or bus clock half phase 2 (LCRR[CLKDIV] = 2), in conjunction with BR n [PS] and LA[24:25].
7 BST4 Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4 (LCRR[CLKDIV]
= 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when LCRR[CLKDIV] = 2.
8–9 G0L General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases 1 and 2
(first half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
3 4 5 6
19 20 21 22
G4T3/
G5T1 G5T3 REDO
WAEN
Figure 10-64. RAM Word Fields
Table 10-40. RAM Word Field Descriptions
7 8 9 10
G0L G0H
All zeros
23 24 25 26
LOOP EXEN AMX
All zeros
Description
Enhanced Local Bus Controller
11 12 13 14
G1T1 G1T3 G2T1
27 28 29 30
NA UTA TODT LAST
15
G2T3
31
10-81