Ddrcdr Field Descriptions; Ddr Debug Configuration; Local Bus Debug Configuration; Ddr Control Driver Register (Ddrcdr) - Freescale Semiconductor MPC8313E Family Reference Manual

5.3.2.7.1

DDR Debug Configuration

The DDR debug configuration enables a DDR memory controller to enter debug mode in which the DDR
SDRAM source ID field and data valid strobe are driven onto one of two optional sets of pins:
• UART pins. UART operation is disabled, and any signals driven by UART devices must be
electrically disconnected from the UART I/O pins. Set SICRL[4–5] to 0b01 to select this mode.
• LBC pins. LBC operation is disabled, and any signals driven by LBC must be electrically
disconnected from the LBC I/O pins. Set SICRL[2–3] to 0b01 to select this mode.
5.3.2.7.2

Local Bus Debug Configuration

The local bus debug configuration enables a LBC debug mode in which the SDRAM source ID field and
data valid strobe for LBC memory accesses are driven onto USB and SPI pins. USB and SPI operation
must be disabled, and any signals driven by USB and SPI devices must be electrically disconnected from
the I/O pins in this case. Set SICRL[6–7] and SICRL[8–9] to 0b10 and SICRL[20–21] to 0b01 to select
this mode.
5.3.2.8

DDR Control Driver Register (DDRCDR)

The DDR control driver register (DDRCDR) contains bits that allow control over the driver of the DDR
SDRAM controller.
DDRCDR is shown in
Offset 0x00128
0 1
R
— DSO_EN
W
Reset 0 0
16
R
W
Reset
Table 5-30 shows the bit definition of the DDRCDR.
Bits Name
0 — Reserved
1 DSO_EN 0 DDR driver software override disable
1 DDR driver software override enable
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 5-16.
2 5 6
DSO_PZ DSO_NZ
0 0 0 0 0 0
Figure 5-16. DDR Control Driver Register (DDRCDR)
Table 5-30. DDRCDR Field Descriptions
9 10 11
—
0 0 0 0
—
All zeros
Description
System Configuration
Access: Read/Write
12 13 14
ODT DDR_cfg —
0 1 0
29 30
M_odr Q_DRN
15
0
31
5-27