Mdeu Fifos; Aesu Mode Register (Aesumr) - Freescale Semiconductor MPC8313E Family Reference Manual

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Security Engine (SEC) 2.2

SHA-1, SHA-224, and SHA-256 are big endian. MD5 is little endian. The

MDEU module internally reverses the endianness of the key upon writing

to or reading from the MDEU key registers if the MDEU mode register

(MDEUMR) indicates that MD5 is the hash of choice.

14.4.2.13 MDEU FIFOs

MDEU uses a private input FIFO to hold data to be hashed. The input FIFO is multiply addressable, but

those multiple addresses point only to the write (push) end of the FIFO. A write to anywhere in the MDEU

FIFO address space causes the 64-bit-words to be pushed onto the MDEU input FIFO, and a read from

anywhere in the MDEU FIFO address space returns all zeros.

SHA-1, SHA-224, and SHA-256 are big endian. MD5 is little endian. The

MDEU module internally reverses the endianness of the key upon writing

to or reading from the MDEU key registers if the MDEU mode register

(MDEUMR) indicates that MD5 is the hash of choice.

Advanced Encryption Standard Execution Unit (AESU)

This section contains details about the advanced encryption standard execution unit (AESU), including

modes of operation, status and control registers, and FIFOs.

Most of the registers described here would not normally be accessed by the host. They are documented

here mainly for debug purposes. In typical operation, the AESU is used through channel-controlled access,

which means that most reads and writes of AESU registers are directed by the SEC channel. Driver

software would perform host-controlled register accesses only on a few registers for initial configuration

and error handling.

The AESU mode register (AESUMR), shown in

AESUMR is cleared when the AESU is reset or re-initialized. Setting a reserved mode bit will generate a

data error. If the mode register is modified during processing, a context error will be generated.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Figure 14-26. AESU Mode Register (AESUMR)

14-26, contains 7 bits that are used to program the

AESU 0x3_4000

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