Hash Function Registers - Freescale Semiconductor MPC8313E Family Reference Manual

15.5.3.7

Hash Function Registers

This section provides detailed descriptions of the registers used for hash functions. All of the registers are
32 bits wide. The DA field of every received frame is processed through a 32-bit CRC generator (CRC-32
polynomial), and the 8 or 9 most significant bits of the CRC are mapped to a hash table entry. The user
can enable a hash entry by setting its bit. A hash entry usually represents a set of addresses. A hash table
hit occurs if the DA CRC result points to an enabled hash entry. Software may need to further filter the
address in order to eliminate false-positive hits in the hash table.
If RCTRL[GHTX] = 0, the 8 most significant bits of the CRC are used as the hash table index. In this case,
registers IGADDR0–IGADDR7 comprise a 256-entry hash table exclusively for individual (unicast)
address matching, while registers GADDR0–GADDR7 comprise a 256-entry hash table for group
(multicast) address matching. If RCTRL[GHTX] = 1, the group hash table is extended to all 512 entries,
and the 9 most significant bits of the CRC are used as the hash table index. In this case, registers
IGADDR0–IGADDR7 hold hash table entries 0–255 for group addresses, while registers
GADDR0–GADDR7 hold entries 256–511 of the extended group hash table.
See Section 15.6.2.7.2, "Hash Table Algorithm,"
15.5.3.7.1 Individual/Group Address Registers 0–7 (IGADDR n )
The IGADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the individual address hash table, or the first 256 entries of the
extended group address hash table used in the address recognition process. The user can enable a hash
entry by setting the appropriate bit. A hash table hit occurs if the DA CRC-32 result points to an enabled
hash entry.
Figure 15-101 describes the definition for the IGADDRn register.
Offset eTSEC1:0x2_4800+4× n ; eTSEC2:0x2_5800+4× n
0
R
W
Reset
Table 15-105 describes the fields of the IGADDRn register.
Bits Name
0–31 IGADDR n Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
IGADDR0 contains entries 0–31 of the 256-entry individual hash table and IGADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, IGADDR0 contains entries 0–31 of the 512-entry extended group hash
table and IGADDR7 represents entries 224–255.
Group Address Registers 0–7 (GADDR n )
15.5.3.7.2
The GADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the group address hash table, or the last 256 entries of the
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
for more information on the hash algorithm.
IGADDR n
Figure 15-101. IGADDR n Register Definition
Table 15-105. IGADDR n Field Descriptions
Enhanced Three-Speed Ethernet Controllers
All zeros
Description
Access: Read/Write
31
15-107