Accessing Internal Memory From External Masters; System Configuration Register Memory Map - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
5.2.11

Accessing Internal Memory from External Masters

In addition to being accessible by the e300 processor, the IMMR memory window is accessible from
external interfaces. This allows external masters on the I/O ports to configure the device.
External masters do not need to know the location of the IMMR memory in the local address map. Rather,
they access this region of the local memory map through a window defined by a register in the interface's
programming model that is accessible to the external master from its external memory map.
The PCI base address for accessing the local IMMR memory is selectable through the PCI internal
memory map register (PIMMR), at offset 0x10, described in
Address Registers (PIBARn)."
by running a PCI configuration cycle. Subsequent memory accesses by a PCI master to the PCI address
range indicated by PIMMR are translated to the local address indicated by the current setting of
IMMRBAR.
5.3 System Configuration
The following sections describe some general information and configuration options that affect system
behavior and performance.
5.3.1

System Configuration Register Memory Map

Table 5-20 shows the memory map for the system configuration registers.
Local
Memory
Offset (Hex)
0x00100 System general purpose register low (SGPRL)
0x00104 System general purpose register high (SGPRH)
0x00108 System part and revision ID register (SPRIDR)
0x0010C Reserved
0x00110 System priority configuration register (SPCR)
0x00114 System I/O configuration register low (SICRL)
0x00118 System I/O configuration register high (SICRH)
0x0011C–0x Reserved
00124
0x00128 DDR control driver register (DDRCDR)
0x0012C DDR debug status register (DDRDSR)
0x00130–0x Reserved
0014C
0x00150–0x Reserved
001FC
1
Depends on the reset configuration word high configuration values.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-16
When the device is a PCI agent, an external PCI master sets this register
Table 5-20. System Configuration Register Memory Map
Register
Section 13.3.2.12, "PCI Inbound Base
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R 0x80B0_0010
— —
R/W 0x0000_0000
0x33FC_00 nn
R/W
R/W
0x0000_0000
— —
R/W 0x0004_0000
R 0x3300_0000
— —
— —
Section/Page
5.3.2.1/5-17
5.3.2.2/5-17
5.3.2.3/5-18
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5.3.2.4/5-18
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5.3.2.5/5-21
5.3.2.6/5-23
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5.3.2.8/5-27
5.3.2.9/5-28
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