Freescale Semiconductor MPC8313E Family Reference Manual page 789

Table 15-35 describes the fields of the RQFPR register.
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1
PID Bit Name
MASK Mask bits to be written to Filer mask_register for masking of property values. The rule match/fail status
0000 0–31
for this PID is determined by RQCTRL[CMP]. Since mask_register is bit-wise ANDed with properties,
every bit of MASK that is cleared also results in the corresponding property bit being cleared in
comparisons. Therefore setting MASK to 0xFFFF_FFFF ensures that all property bits participate in rule
matches.
0001 0–13 — Reserved
14 AR Set if an ARP response packet is seen.
15 ARQ Set if an ARP request packet is seen.
16 EBC Set if the destination Ethernet address is to the broadcast address.
17 VLN Set if a VLAN tag (Ethertype DFVLAN[TAG] or 0x8100) was seen in the frame.
18 CFI Set to the value of the Canonical Format Indicator in the VLAN control tag if VLAN is set, zero otherwise.
19 JUM Set if a jumbo Ethernet frame was parsed.
20 IPF Set if a fragmented IPv4 or IPv6 header was encountered.
See the descriptions of receive FCB fields IP and PRO in
more information on determining the status of received packets for which IPF is set.
21 — Reserved
22 IP4 Set if an IPv4 header was parsed.
23 IP6 Set if an IPv6 header was parsed.
24 ICC Set if the IPv4 header checksum was checked.
25 ICV Set if the IPv4 header checksum was verified correct.
26 TCP Set if a TCP header was parsed.
27 UDP Set if a UDP header was parsed.
28–29 — Reserved.
30 PER Set on a parse error, such as header inconsistency.
31 EER Set on an Ethernet framing error that prevents parsing.
0010 0–7 ARB User-defined arbitrary bit field property: byte 0 extracted. Defaults to 0x00.
8–15 User-defined arbitrary bit field property: byte 1 extracted. Defaults to 0x00.
16–23 User-defined arbitrary bit field property: byte 2 extracted. Defaults to 0x00.
24–31 User-defined arbitrary bit field property: byte 3 extracted. Defaults to 0x00.
0011 0–7 — Reserved, should be written with zero.
8–31 DAH Destination MAC address, most significant 24 bits. Defaults to 0x000000.
0100 0–7 — Reserved, should be written with zero.
8–31 DAL Destination MAC address, least significant 24 bits. Defaults to 0x000000.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-35. RQFPR Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
Section 15.6.3.3, "Receive Path Off-Load," for
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