Relaxed Timing - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Local Bus Controller
CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in
LCRR[CLDIV] = 2, LWEn is negated either coincident with LCSn or one cycle earlier.
1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWEn is affected
independent of ACS.
2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal
case provided that LCRR[CLDIV] = 4 or 8.
3. TRLX = 1 in conjunction with CSNT = 1, negates the LCSn and LWEn 1 + 1/4 cycle earlier if
LCRR[CLKDIV] = 4 or 8.
If LCRR[CLKDIV] = 2, LCSn and LWEn are negated either normally or one cycle earlier if TRLX = 1.
For example, when ACS = 00, CSNT = 1 and TRLX = 0, LWEn is negated one quarter of a clock earlier
and LCSn is negated normally as shown in
10.4.2.3.3

Relaxed Timing

ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
• An additional bus cycle is added between the address and control signals (but only if ACS is not
equal to 00).
• The number of wait states specified by SCY is doubled, providing up to 30 wait states.
• The extended hold time on read accesses (EHTR) is extended further.
• LCSn signals are negated one cycle earlier during writes (but only if ACS is not equal to 00).
• LWE[0:1] signals are negated one cycle earlier during writes.
Figure 10-37 and Figure 10-38
LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-52
Figure 10-36.
show relaxed timing read and write transactions. The effect of
Figure 10-36. If
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