Dma Control Register (Dmactrl) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Offset eTSEC1:0x2_4028; eTSEC2:0x2_5028
0
R
W
Reset
Table 15-13 describes the fields of the PTV register.
Bits Name
0–15 PTE Extended pause control. This field allows software to add a 16-bit additional control parameter into the PAUSE
frame to be sent when TCTRL[TFC_PAUSE] is set. Note that current IEEE 802.3 PAUSE frame format
requires this parameter to be cleared.
16–31 PT Pause time value. Represents the 16-bit pause quanta (that is, 512 bit times). This pause value is used as
part of the PAUSE frame to be sent when TCTRL[TFC_PAUSE] is set. See
on page 15-154
15.5.3.1.8

DMA Control Register (DMACTRL)

DMACTRL is writable by the user to configure the DMA block.
the DMACTRL register.
Offset eTSEC1:0x2_402C; eTSEC2:0x2_502C
0
R
W
Reset
Table 15-14 describes the fields of the DMACTRL register.
Bits Name
0–15 — Reserved
16 LE Little-endian descriptor mode enable. This bit controls both the reading and writing of descriptors; data
buffers are always transferred in network byte order.
0 RxBDs and TxBDs are interpreted with big-endian byte ordering, as shown in
Buffer Descriptors."
1 RxBDs and TxBDs are interpreted with little-endian byte ordering. That is, the 16 bits of flags are
considered a complete half-word unit, the buffer length is considered another complete half-word unit, and
the buffer pointer is considered a complete word unit.
17–23 — Reserved
24 TDSEN Tx Data snoop enable.
0 Disables snooping of all transmit frames from memory.
1 Enables snooping of all transmit frames from memory.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-34
PTE
Figure 15-8. PTV Register Definition
Table 15-13. PTV Field Descriptions
for more information.
15 16 17
— LE
Figure 15-9. DMACTRL Register
Table 15-14. DMACTRL Field Descriptions
15 16
All zeros
Description
Figure 15-9
23 24 25
— TDSEN TBDSEN — GRS GTS TOD WWR WOP
All zeros
Description
Access: Read/Write
PT
Section 15.6.2.9, "Flow Control,"
describes the definition for
Access: Read/Write
26 27 28 29 30
Section 15.6.7.1, "Data
Freescale Semiconductor
31
31