System Internal Interrupt Group A Priority Register (Siprr_A) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments (continued)
Table 8-10 defines the bit fields of SIPNR_L.
Bits Name
0–31 INT n Each implemented bit (listed in
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user
clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
8.5.4

System Internal Interrupt Group A Priority Register (SIPRR_A)

SIPRR_A, shown in Figure
receive request (TSEC1 Rx), TSEC1 transmit/receive error (TSEC1 Err), TSEC2 transmit request (TSEC2
Tx), TSEC2 receive request (TSEC2 Rx) TSEC2 transmit/receive error (TSEC2 Err), USB DR, internal
interrupt signals.
For more information, see
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Bits
10
11
12
13
14
15
16
17–19
20
21
22–25
26
27
28–30
31
Table 8-10. SIPNR_L Field Descriptions
Table 8-9) corresponds to an internal interrupt source. When an interrupt is
8-6, defines the priority between TSEC1 transmit request (TSEC1 Tx), TSEC1
Section 8.6.3, "Internal Interrupts Group Relative Priority."
Integrated Programmable Interrupt Controller (IPIC)
Field
GPIO
—
DDR
LBC
GTM2
GTM6
PMC
—
GTM3
GTM7
—
GTM1
GTM5
—
—
Description
8-13