Immr Memory Map - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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In certain specific cases, reserved bits should not be cleared but should keep their reset value. Thus, the

software should perform a 'read-modify-write' and make sure that it does not change the reset value of

those bits. The description of the specific bits will indicate when this is needed.

0x0_0000–0x0_01FF

0x0_0200–0x0_02FF

0x0_0300–0x0_03FF

0x0_0400–0x0_04FF

0x0_0500–0x0_05FF

0x0_0600–0x0_06FF

0x0_0700–0x0_07FF

0x0_0800–0x0_08FF

0x0_0900–0x0_09FF

0x0_0A00–0x0_0AFF

0x0_0B00–0x0_0BFF

0x0_0C00–0x0_0CFF

0x0_0D00–0x0_0DFF

0x0_0E00–0x0_0EFF

0x0_0F00–0x0_0FFF

0x0_1000–0x0_10FF

0x0_1100–0x0_11FF

0x0_1200–0x0_12FF

0x0_1300–0x0_13FF

0x0_1400–0x0_17FF

0x0_1800–0x0_1BFF

0x0_1C00–0x0_1FFF

0x0_2000–0x0_2FFF

0x0_3000–0x0_30FF

0x0_3100–0x0_31FF

0x0_3200–0x0_32FF

0x0_3300–0x0_33FF

0x0_3400–0x0_37FF

0x0_3800–0x0_3BFF

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Table 2-1. IMMR Memory Map

System configuration

Watchdog timer

Real time clock

Periodic interval timer

Global timers module 1

Global timers module 2

Integrated programable

System arbiter

Reset module

Clock module

Power management

C1 controller

C2 controller

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