System Internal Interrupt Control Register (Sicnr) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Table 8-13 defines the bit fields of SIMSR_H.
Bits Name
INT n Each implemented bit (listed in
0–31
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enable) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
• SIMSR bit positions do not change according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
unmasked events in the corresponding event register.
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
Unimplemented bits, shown as reserved in
Figure 8-9 shows SIMSR_L.
Offset 0x24
0
R
W
Reset
Figure 8-9. System Internal Interrupt Mask Register (SIMSR_L)
Table 8-14 defines the bit fields of SIMSR_L.
Bits Name
INT n Each implemented bit (listed in
0–31
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enabled) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
• SIMSR bit positions are not changed according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all unmasked
events in the corresponding event register.
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error
Unimplemented bits, shown as reserved in
8.5.7

System Internal Interrupt Control Register (SICNR)

SICNR, shown in Figure
SYSA0–SYSA1 and SYSD0–SYSD1 priority positions. All other priority positions assert int to the core.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-16
Table 8-13. SIMSR_H Field Descriptions
Table 8-7) corresponds to an external interrupt source. The user masks an
INT n (Implemented bits are listed in
Table 8-14. SIMSR_L Field Descriptions
Table 8-9) corresponds to an external interrupt source. The user masks an
8-10, defines the IPIC output interrupt type (int, cint, or smi) in the
Description
Table 8-7, are ignored on writes; read = 0.
Table
All zeros
Description
Figure 8-9, are ignored on writes; read = 0.
Access: Read/write
8-9.)
Freescale Semiconductor
31