Freescale Semiconductor MPC8313E Family Reference Manual page 601

Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_PERR I/O PCI parity error
O
I
PCI_PME I/O PCI PME signal
O
I
PCI_REQ0 I/O PCI bus request
O
I
PCI_REQ[1:2] I
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Outputs for the bi-directional parity error.
State Asserted—The PCI controller, acting as a PCI agent, detected a data parity error. (driven
Meaning by the PCI initiator on reads; driven by the PCI target on writes.)
Negated—No error.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional parity error.
State Asserted—Another PCI agent detects a data parity error while this PCI controller is
Meaning sourcing data (this PCI controller was acting as the PCI initiator during a write, or is
acting as the PCI target during a read).
Negated—No error.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional PCI_PME signal. This is an open-drain signal.
State Asserted—Indicates that a power management event has occurred
Meaning Negated—Indicates that no power management event has occurred
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional PCI_PME signal.
State Asserted—Indicates an agent is requesting a power state change
Meaning Negated—Indicates no power state change request
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
.
Input signal on this PCI controller when the arbiter is enabled. Output signal when
the arbiter is disabled. Note that PCI_REQ n is a point-to-point signal. Every master has its own bus
request signal.
Outputs for the bi-directional bus request.
State Asserted—The PCI controller is requesting control of the PCI bus to perform a
Meaning transaction.
Negated—The PCI controller does not require use of the PCI bus.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Input for the bi-directional bus request.
State Asserted—Agent 0 is requesting control of the PCI bus to perform a transaction.
Meaning Negated—Agent 0 does not require use of the PCI bus.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
.
PCI bus request Input signals on this PCI controller when the arbiter is enabled. Note that
PCI_REQ[n] is a point-to-point signal. Every master has its own bus request signal. Following is the
state meaning for the PCI_REQ[n] input.
Asserted—An agent n is requesting control of the PCI bus to perform a transaction.
State
Meaning Negated—An agent n does not require use of the PCI bus.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Description
PCI Bus Interface
13-9