Freescale Semiconductor MPC8313E Family Reference Manual page 615

outbound window, or where an outbound translation window points back into an inbound window, are not
allowed.
Offset 0x38 (n=2)
0x50 (n=1)
0x68 (n=0)
0
R
W
Reset
Figure 13-15. PCI Inbound Translation Address Registers (PITAR n )
Table 13-18 shows the bit settings of PITARn.
Bits Name
0–11 —
12–31 TA
13.3.2.12 PCI Inbound Base Address Registers (PIBAR n )
PIBARn contains fields for defining the starting point of the inbound windows in the PCI memory space.
A write to a PIBARn register also causes a change in the base address bits in the corresponding GPL base
address register in the PCI configuration space.
Offset 0x40 (n=2)
0x58 (n=1)
0x70 (n=0)
0
R
W
Reset
Table 13-19 shows the bit settings of PIBARn.
Bits Name
0–31 BA
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
11 12
—
Table 13-18. PITAR n Field Descriptions
Reserved
Translation address. Contains the starting address of the inbound translated address. TA
corresponds to the 20 highest-order bits of a 32-bit local address. The specified address must be
aligned to the window size, as defined by PIWAR n [IWS].
Figure 13-16. PCI Inbound Base Address Registers (PIBAR n )
Table 13-19. PIBAR n Field Descriptions
Base address. Contains the starting address in the PCI memory space of the inbound window. This
field corresponds to bits 43–12 of a 64-bit address. In PIBAR0, the upper 12 bits are reserved
because only a 32-bit address is supported. The specified address must be aligned to the window
size, as defined by PIWAR n [IWS].
All zeros
Description
Figure 13-16 shows the PIBARx fields.
BA
All zeros
Description
PCI Bus Interface
Access: Read/Write
TA
Access: Read/Write
31
31
13-23