Freescale Semiconductor MPC8313E Family Reference Manual page 746

Enhanced Three-Speed Ethernet Controllers
eTSEC1
Offset
0x2_4404 RBASE0—RxBD base address of ring 0
0x2_4408 Reserved
0x2_440C RBASE1*—RxBD base address of ring 1
0x2_4410 Reserved
0x2_4414 RBASE2*—RxBD base address of ring 2
0x2_4418 Reserved
0x2_441C RBASE3*—RxBD base address of ring 3
0x2_4420 Reserved
0x2_4424 RBASE4*—RxBD base address of ring 4
0x2_4428 Reserved
0x2_442C RBASE5*—RxBD base address of ring 5
0x2_4430 Reserved
0x2_4434 RBASE6*—RxBD base address of ring 6
0x2_4438 Reserved
0x2_443C RBASE7*—RxBD base address of ring 7
0x2_4440– Reserved
0x2_44BC
0x2_44C0 TMR_RXTS_H* - Rx timer time stamp register high
0x2_44C4 TMR_RXTS_L* - Rx timer time stamp register low
0x2_44C8– Reserved
0x2_44FC
0x2_4500 MACCFG1—MAC configuration register 1
0x2_4504 MACCFG2—MAC configuration register 2
0x2_4508 IPGIFG—Inter-packet/inter-frame gap register
0x2_450C HAFDUP—Half-duplex control
0x2_4510 MAXFRM—Maximum frame length
0x2_4514– Reserved
0x2_451C
0x2_4520 MIIMCFG—MII management configuration
0x2_4524 MIIMCOM—MII management command
0x2_4528 MIIMADD—MII management address
0x2_452C MIIMCON—MII management control
0x2_4530 MIIMSTAT—MII management status
0x2_4534 MIIMIND—MII management indicator
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-16
Table 15-4. Module Memory Map (continued)
1
Name
eTSEC MAC Registers
2
Access Reset
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
R/W All zeros
— —
R/W All zeros
R/W 0x0000_7000
R/W 0x4060_5060
R/W 0x00A1_F037
R/W 0x0000_0600
— —
R/W 0x0000_0007
R/W All zeros
R/W All zeros
WO All zeros
R All zeros
R All zeros
Freescale Semiconductor
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