Ddr Sdram Interval Configuration (Ddr_Sdram_Interval); Ddr Sdram Data Initialization (Ddr_Data_Init) - Freescale Semiconductor MPC8313E Family Reference Manual

9.4.1.12

DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)

The DDR SDRAM interval configuration register, shown in
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Offset 0x124
0
R
W
Reset
Figure 9-13. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
Table 9-18 describes the DDR_SDRAM_INTERVAL fields.
Bits Name
0–15 REFINT Refresh interval
Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes are not issued when the REFINT is set to all 0s.
16–17 — Reserved
18–31 BSTOPRE Precharge interval
Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM access. If BSTOPRE
is zero, the DDR memory controller uses auto-precharge read and write commands rather than operating in
page mode. This is called global auto-precharge mode.
9.4.1.13

DDR SDRAM Data Initialization (DDR_DATA_INIT)

The DDR SDRAM data initialization register, shown in
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Offset 0x128
0
R
W
Reset
Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Table 9-19 describes the DDR_DATA_INIT fields.
Bits Name
0–31 INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT]
is set.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
REFINT
Table 9-18. DDR_SDRAM_INTERVAL Field Descriptions
Table 9-19. DDR_DATA_INIT Field Descriptions
Figure 9-13, sets the number of DRAM clock
15 16 17 18
—
All zeros
Description
Figure 9-14, provides the value that is used to
INIT_VALUE
All zeros
Description
DDR Memory Controller
Access: Read/Write
31
BSTOPRE
Access: Read/Write
31
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