Freescale Semiconductor MPC8313E Family Reference Manual page 740

Enhanced Three-Speed Ethernet Controllers
Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
Signal I/O
TSEC n _RX_ER
TSEC n _TX_CLK
TSEC n _TXD[3:0] O
TSEC n _TX_EN O
TSEC n _TX_ER O
TSEC_1588_CLK
TSEC_1588_GCLK O
TSEC_1588_TRIG1
TSEC_1588_TRIG2
TSEC_1588_PP1 O
TSEC_1588_PP2 O
TSEC_1588_PP3 O
TSEC_1588_ALARM1 O
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-10
I Receive error
State Asserted/Negated—In MII, or RMII mode, if TSEC n _RX_ER and TSEC n _RX_DV are
Meaning asserted, the PHY has detected an error in the current frame.
This signal is not used in the RTBI or RGMII modes.
Transmit clock in. In MII mode, TSEC n _TX_CLK is a continuous clock (2.5 or 25 MHz) that
I
provides a timing reference for the TSEC n _TX_EN, TSEC n _TXD, and TSEC n _TX_ER signals.
_In RMII mode this signal is the reference clock shared between transmit and receive, and is
supplied by the PHY.
This signal is not used in the eTSEC RTBI or RGMII modes.
Transmit data out. DVIn MII mode, TSEC n _TXD[3:0] represent a nibble of data to be sent from
the MAC to the PHY when TSEC n _TX_EN is asserted and have no meaning while
TSEC n _TX_EN is negated.
In RGMII or RTBI mode, data bits 3:0 are transmitted on the rising edge of TSEC n _GTX_CLK,
and data bits 7:4 are transmitted on the falling edge of TSEC n _GTX_CLK.
In RMII mode TSEC n _TXD[1:0] represents TXD[1:0], which is valid data sent to the PHY when
TSEC n _TX_EN is asserted, or undefined otherwise.
Note that some of these signals are also used during reset to configure the eTSEC interface
mode.
Transmit data valid. In MII, or RMII mode, if TSEC n _TX_EN is asserted, the MAC is indicating
that valid data is present on the MII's TSEC n _TXD signals.
In RGMII mode, TSEC n _TX_EN becomes TX_CTL. TX_EN and TX_ERR are asserted on this
signal on rising and falling edges of the TSEC n _GTX_CLK, respectively.
In RTBI mode, TSEC n _TX_EN represents TCG[4] on the rising edge and TCG[9] on the falling
edge of TSEC n _GTX_CLK, respectively. Together with TCG[3:0] and TCG[8:5], they represent
the 10-bit encoded symbol.
Transmit error. In MII mode, assertion of TSEC n _TX_ER for one or more clock cycles while
TSEC n _TX_EN is asserted causes the PHY to transmit one or more illegal symbols. Asserting
TSEC n _TX_ER has no effect while operating at 10 Mbps or while TSEC n _TX_EN is negated.
This signal transitions synchronously with respect to TSEC n _TX_CLK.
This signal is not used in the eTSEC RMII, RTBI, or RGMII modes and is driven low.
I 1588 clock in. External high precision timer reference clock input (chip external input pin).
1588 clock out. Phase aligned timer clock divider output (chip external output pin).
I 1588 trigger in 1. External timer trigger input 1.This is an asynchronous general purpose input
(chip external input pin).
I 1588 trigger in 2. External timer trigger input 2.This is an asynchronous general purpose input
(chip external input pin).
1588 pulse out 1. Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external
output pin)
1588 pulse out 2. Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external
output pin)
1588 pulse out 3. Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external
output pin)
1588 timer alarm 1. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin)
Description
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