System Clock Control Register (Sccr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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4.5.2.3

System Clock Control Register (SCCR)

SCCR, shown in
Figure
Address 0x0_0A08
0
1
R
TSECCM
TSEC1ON TSEC2ON
W
Reset
0
1
16
R
W
Reset
Table 4-36
defines the bit fields of SCCR.
Bits
Name
0–1
TSECCM
2
TSEC1ON
3
TSEC2ON
4–5
6–7
ENCCM
8–9
10–11
USB
DRCM
12–14
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
4-15, controls device units that have a configurable clock ratio.
2
3
4
1
1
1
Figure 4-15. System Clock Control Register (SCCR)
Table 4-36. SCCR Bit Descriptions
TSEC1 and TSEC2 clock mode.
00 Reserved. Write not allowed. If written, treated as ratio 1:1.
01 TSEC1&2 clock/ csb_clk ratio is 1:1.
10 TSEC1&2 clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than TSEC1&2).
11 TSEC1&2 clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than TSEC1&2).
TSEC1 clock switch off
0 TSEC1 clock is disabled.
1 TSEC1 clock is enabled and in the ratio as specified by TSECCM.
TSEC2 clock switch off
0 TSEC2 clock is disabled.
1 TSEC2 clock is enabled and in the ratio as specified by TSECCM.
Reserved
Encryption core, JTAG, and I
00 Encryption core clock is disabled.
01 Encryption core clock/ csb_clk ratio is 1:1.
10 Encryption core clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the encryption core).
11 Encryption core clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the encryption core).
Note: The encryption core must have the same clock ratio as the USB unit, unless one of them has
its clock disabled.
Reserved
USB DR clock mode.
00 USB DR clock is disabled.
01 USB DR clock/ csb_clk ratio is 1:1.
10 USB DR clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the USB DR).
11 USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR).
Reserved
5
6
7
8
9
ENCCM
1
0
1
1
1
All ones
Description
2
C1 clock mode.
Reset, Clocking, and Initialization
Access: Read/Write
10
11
12
USBDRCM
0
1
1
1
14
15
PCICM
1
1
31
4-39

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