Upm Programming Example (Two Sequential Reads From The Ram Array); Upm Signal Timing - Freescale Semiconductor MPC8313E Family Reference Manual

Note that if steps 1 and 2 or steps 6 and 7 are reversed, step 3 or 8 (as appropriate) is replaced by the
following:
• Read MxMR to ensure that the MxMR has already been updated with the desired configuration.
10.4.4.2.2

UPM Programming Example (Two Sequential Reads from the RAM Array)

RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (MxMR[OP] = 0b10). The following example further
illustrates the steps required to perform two reads from the RAM array at non-sequential addresses
assuming that the relevant BRn and ORn registers have been previously set up:
1. Program MxMR for the first read with the desired RAM array address.
2. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
such as RAM array address.
3. Perform a dummy read transaction.
4. Read/check MxMR[MAD]. If incremented, the previous dummy read transaction is completed;
proceed to step 5. Repeat step 4 until incremented.
5. Read MDR.
6. Program MxMR for the second read with the desired RAM array address.
7. Read MxMR to ensure that the MxMR has already been updated with the desired configuration,
such as RAM array address.
8. Perform a dummy read transaction.
9. Read/check MxMR[MAD]. If incremented, the previous dummy read transaction is completed;
proceed to step 10. Repeat step 9 until incremented.
10. Read MDR.
10.4.4.3

UPM Signal Timing

RAM word fields specify the value of the various external signals at a granularity of up to four values for
each bus clock cycle. The signal timing generator causes external signals to behave according to timing
specified in the current RAM word. For LCRR[CLKDIV] = 4 or 8, each bit in the RAM word relating to
LCSn and LBS timing specifies the value of the corresponding external signal at each quarter phase of the
bus clock. If LCRR[CLKDIV] = 2, the external signal can change value only on each half phase of the bus
clock. If the RAM word in this case (LCRR[CLKDIV] = 2) specifies a quarter phase signal change, the
signal timing generator interprets this as a half cycle change.
The division of UPM bus cycles into phases is shown in
LCRR[CLKDIV] = 2, the bus cycle comprises only two active phases, T1 and T3, which correspond with
the first and second halves of the bus clock cycle, respectively. However, if LCRR[CLKDIV] = 4 or 8, four
phases, T1–T4, define four quarters of the bus clock cycle. Because T2 and T4 are inactive when
LCRR[CLKDIV] = 2, UPM ignores signal timing programmed for assertion in either of these phases in
the case LCRR[CLKDIV] = 2.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 10-61 and Figure
Enhanced Local Bus Controller
10-62. If
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