Crypto-Channel Current Descriptor Pointer Register (Cdpr); Fetch Fifo (Ff) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Security Engine (SEC) 2.2
Table 14-36. Crypto-Channel Pointer Status Register PAIR_PTR Field Values (continued)
Value
0x03
0x04
0x05
0x06
0x07
0x08–FF
14.5.1.3

Crypto-Channel Current Descriptor Pointer Register (CDPR)

The crypto-channel current descriptor pointer register (CDPR), shown in
address of the descriptor which the channel is currently processing.
0
Field
Reset
R/W
Addr
Figure 14-38. Crypto-Channel Current Descriptor Pointer Register (CDPR)
The bits in the CDPR perform the functions described in
Bits
Names
0–31
32–63
CUR_DES_PTR_ADRS Current descriptor pointer address. Pointer to system memory location of the current
14.5.1.4

Fetch FIFO (FF)

The channel contains a fetch FIFO to store a queue of pointers to descriptors that the channel will process.
The fetch FIFO, displayed in
processed. In typical operation, the host CPU will create a descriptor in memory containing all relevant
mode and location information for the SEC, then 'launch' the SEC by writing the address of the descriptor
to the fetch FIFO.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-62
Processing pointer dword 3
Processing pointer dword 4
Processing pointer dword 5
Processing pointer dword 6
Complete (or not yet begun) processing of header dword and pointer dwords
Reserved
Table 14-37. CDPR Field Descriptions
Reserved, set to zero.
descriptor. This field reflects the starting location in system memory of the descriptor
currently loaded into the DB. This value is updated whenever the channel requests a fetch
of a descriptor from the controller.
The value from the fetch FIFO is transferred to the current descriptor pointer register
immediately after the fetch is completed.
This address will be used as the destination for writeback of the modified header dword, if
header writeback notification is enabled.
Figure
14-39, contains the addresses of the first byte of descriptors to be
Error
31
32
CUR_DES_PTR_ADRS
0x0000_0000
R
Channel_1 0x3_1140
Table
14-37.
Description
Figure
14-38, contains the
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