Transaction Termination - Freescale Semiconductor MPC8313E Family Reference Manual

Figure 13-51 shows an example of a burst write transaction.
PCI_CLK
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
A write transaction is similar to a read transaction except no turnaround cycle is needed following the
address phase because the initiator provides both address and data. Data phases are the same for both read
and write transactions.
13.4.3.8

Transaction Termination

The termination of a PCI transaction is orderly and systematic, regardless of the cause of the termination.
All transactions end when PCI_FRAME and PCI_IRDY are both negated, indicating the idle cycle.
The PCI controller as an initiator terminates a transaction when PCI_FRAME is negated and PCI_IRDY
is asserted. This indicates that the final data phase is in progress. The final data transfer occurs when both
PCI_TRDY and PCI_IRDY are asserted. A master-abort is an abnormal case of a master initiated
termination. If the PCI controller detects that PCI_DEVSEL has remained negated for more than four
clocks after the assertion of PCI_FRAME, it negates PCI_FRAME and then, on the next clock, negates
PCI_IRDY. On aborted reads, the PCI controller returns 0xFFFF_FFFF. The data is lost on aborted writes.
When the PCI controller as a target needs to suspend a transaction, it asserts PCI_STOP. Once asserted,
PCI_STOP remains asserted until PCI_FRAME is negated. Depending on the circumstances, data may or
may not be transferred during the request for termination. If PCI_TRDY and PCI_IRDY are asserted
during the assertion of PCI_STOP, data is transferred. This type of target-initiated termination is called a
disconnect B, shown in
PCI_IRDY is not, PCI_TRDY must remain asserted until PCI_IRDY is asserted and the data is
transferred. This is called a disconnect A target-initiated termination, also shown in
However, if PCI_TRDY is negated when PCI_STOP is asserted, no more data is transferred, and the
initiator therefore does not have to wait for a final data transfer (see the retry diagram in
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
ADDR DATA1
CMD BEs 1
Figure 13-51. Burst Write Example
Figure 13-52. If PCI_TRDY is asserted when PCI_STOP is asserted but
DATA2 DATA3 DATA4
BEs 2 BEs 3 BEs 4
PCI Bus Interface
Figure 13-52.
Figure 13-50).
13-51