System External Interrupt Mask Register (Semsr) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Table 8-18 defines the bit fields of SMPRR_B.
Bits Name
MIXB n P MIXB n priority order. Defines which interrupt source asserts its request in the MIXB n priority position. The
0–2
3–11, user must not program the same code to more than one priority position (0–7). These bits can be changed
16–27 dynamically. The definition of MIXB n P is as follows:
000 RTC ALR asserts its request to the MIXB n position.
001 MU asserts its request to the MIXB n position.
010 SBA asserts its request to the MIXB n position.
011 DMA asserts its request to the MIXB n position.
100 IRQ4 asserts its request to the MIXB n position.
101–111 Reserved
12–15, — Write ignored, read = 0
28–31
8.5.11

System External Interrupt Mask Register (SEMSR)

Each bit in the system external interrupt mask register (SEMSR), shown in
external interrupt source. The user masks an interrupt by clearing the corresponding SEMSR bit. An
interrupt is unmasked (enabled) by setting the corresponding SEMSR bit.
When an external interrupt request occurs, the corresponding SEPNR bit is set regardless of the setting of
the corresponding SEMSR bit. However, if the corresponding SEMSR bit is cleared, no interrupt request
is passed to the core.
When an SEMSR bit is cleared by the user at the same time that an interrupt source requests an interrupt
service, the request stops. If the user sets the SEMSR bit later, a previously pending interrupt request is
processed by the core according to its assigned priority. SEMSR can be read by the user at any time.
Offset 0x38
0 1 2
R
1
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
W
Reset
16 17
R
SIRQ0
W
Reset
1
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
Figure 8-14. System External Interrupt Mask Register (SEMSR)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-20
Table 8-18. SMPRR_B Field Descriptions
3 4 5
Description
—
All zeros
—
All zeros
Figure 8-11, corresponds to an
Access: Read/write
Freescale Semiconductor
15
31