Ddrdsr Field Descriptions; Software Watchdog Timer (Wdt); Wdt Overview - Freescale Semiconductor MPC8313E Family Reference Manual

Table 5-31 shows the bit settings of the DDRDSR.
Bits Name
0–1 — Reserved
2–5 PZ Current setting of PFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
6–9 NZ Current setting of NFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
10–31 — Reserved
5.4

Software Watchdog Timer (WDT)

The following sections describe the theory of operation of the software watchdog timer (WDT) in the
device, including a definition of the external signals and the functions they serve. Additionally, the
configuration, control, and status registers are also described. Note that individual chapters in this book
describe specific initialization aspects for each individual block.
5.4.1

WDT Overview

The device provides a software watchdog timer (WDT) feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The watchdog counter is a free-running down-counter that generates a reset or a non-maskable interrupt
on underflow. To prevent a reset, software must periodically restart the countdown. The WDT is
responsible for asserting a hardware reset or machine-check interrupt (mcp) if the software fails to service
the software watchdog timer for a certain period of time (for example, because software is lost or trapped
in a loop with no controlled exit).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-31. DDRDSR Field Descriptions
Description
System Configuration
5-29