Freescale Semiconductor MPC8313E Family Reference Manual page 710

Powerquicc ii pro integrated processor
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Security Engine (SEC) 2.2
Bits
Names
56
IWSE
ICV writeback status enable
0 No special action.
1 If the descriptor calls for ICV comparison, then at the completion of descriptor processing, write back the
status of all EUs into the header dword.
57
AWSE Always writeback status enable
0 No special action.
1 At the completion of processing each descriptor, write back the status of all EUs into the header dword. In
this case, IWSE has no effect.
59
CDWE Channel done writeback enable
0 Channel done writeback disabled.
1 Channel done writeback enabled. Upon completion of descriptor processing, if the NT bit is set for Global,
or if the DN (Done Notification) bit is set in the header word of the descriptor, notify the host by writing back
the descriptor header with the writeback information shown in
memory location of the original descriptor header to determine if that descriptor has been completed.
60
Reserved, set to zero
61
NT
Notification type. This bit controls when the channel will generate channel done notification. Channel done
notification can take the form of an interrupt or modified header writeback or both, depending on the state of
the CDIE and CDWE control bits.
0 Global notification. The channel will generate channel done notification (if enabled) at the end of each
descriptor.
1 Selected notification. The channel will generate channel done notification (if enabled) at the end of every
descriptor with the DONE bit set in the descriptor header.
62
CDIE
Channel done interrupt enable
0 Channel done interrupt disabled
1 Channel Done Interrupt enabled. Upon completion of descriptor processing, if the NT bit is set for Global,
or if the DN (Done Notification) bit is set in the header word of the descriptor, then notify the host by
asserting an interrupt.
Refer to
63
Reserved, set to zero
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-56
Table 14-31. CCCR Field Descriptions (continued)
Section 14.5.2, "Channel
Interrupts," for complete description of channel interrupt operation.
Description
Table
14-5. This enables the host to poll the
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