Asynchronous List Queue Head Pointer; Isochronous (High-Speed) Transfer Descriptor (Itd) - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
schedule. The least-significant bits in a frame list pointer are used to key the host controller in as to the
type of object the pointer is referencing.
The least-significant bit is the T bit (bit 0). When this bit is set, the host controller never uses the value of
the frame list pointer as a physical memory pointer. The Typ field indicates the exact type of data structure
being referenced by this pointer. The value encodings for the Typ field are given in
16.5.2

Asynchronous List Queue Head Pointer

The asynchronous transfer list (based at the ASYNCLISTADDR register) is where all the control and bulk
transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the
periodic list is disabled, or the periodic list is empty.
organization.
AsyncListAddr
The asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply
a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked
into the asynchronous list.
16.5.3

Isochronous (High-Speed) Transfer Descriptor (iTD)

Figure 16-38 illustrates the format of an isochronous transfer descriptor. This structure is used only for
high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs
must be aligned on a 32-byte boundary.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Table 16-39. Typ Field Encodings
Typ
00 Isochronous transfer descriptor
01 Queue head
10 Split transaction isochronous transfer descriptor
11 Frame span traversal node
Operational
Registers
Figure 16-37. Asynchronous Schedule Organization
Description
Figure 16-37 shows the asynchronous schedule
Bulk/Control Queue Heads
H
Table 16-39.
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