Power Port; Reporting Over-Current - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
2. Optionally modify the BURSTSIZE register.
3. Program the PTS field of the PORTSC register if using a non-ULPI PHY.
4. Set CONTROL[USB_EN].
5. Write the appropriate value to the USBINTR register to enable the appropriate interrupts.
6. Write the base address of the periodic frame list to the PERIODICLIST BASE register. If there are
no work items in the periodic schedule, all elements of the periodic frame list should have their
T-Bits set.
7. Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable) and
turn on the controller by setting the RS bit.
At this point, the USB DR module is up and running and the port registers begin reporting device connects.
System software can enumerate a port through the reset process (where the port is in the enabled state). At
this point, the port is active with SOFs occurring down the enabled high-speed ports, but the schedules
have not yet been enabled. The EHCI host controller will not transmit SOFs to enabled Full- or Low-speed
ports.
In order to communicate with devices via the asynchronous schedule, system software must write the
ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by writing a one to USBCMD[ASE]. In order to communicate with devices via
the periodic schedule, system software must enable the periodic schedule by writing a one to
USBCMD[PSE]. Note that the schedules can be turned on before the first port is reset (and enabled).
Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved,
depending on the intended operation.
16.6.2

Power Port

The HCSPARAMS[PPC] bit indicates whether the USB 2.0 host controller has port power control. When
the PPC bit is set, the host controller supports port power switches. Each available switch has an output
enable. PPE is controlled based on the state of the combination bits—PPC bit, EHCI Configured (CF)-bit
and individual Port Power (PP) bit. The Configured Flag and Port Power Control bits are always 1'b1 in
Host Mode. The PPE always follows the state of Port Power (PP) bit that is, if PP is 0, PPE will be 0 and
if PP is 1, PPE will be 1.
16.6.3

Reporting Over-Current

Host ports by definition are power providers on USB. Whether the ports are considered high- or
low-powered is a platform implementation issue. The EHCI PORTSC register has an over-current status
and over-current change bit. The functionality of these bits is specified in the USB Specification Revision
2.0.
The over current detection and limiting logic resides outside the DR logic. The over-current condition
effects the following bits in the PORTSC register on the EHCI port:
• Over-current active bit (OCA) is set. When the over-current condition goes away, the OCA will
transition from a one to a zero.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-70 Freescale Semiconductor