Freescale Semiconductor MPC8313E Family Reference Manual page 65

Table
Number
14-3 SEC Address Map................................................................................................................. 14-9
14-4 Header Dword Bit Definitions ............................................................................................ 14-12
14-5 Header Dword Writeback Bit Definitions........................................................................... 14-13
14-6 EU_SEL0 and EU_SEL1 Values ........................................................................................ 14-13
14-7 Descriptor Types ................................................................................................................. 14-14
14-8 Pointer Dword Field Definitions......................................................................................... 14-15
14-9 Link Table Field Definitions ............................................................................................... 14-17
14-10 Descriptor Format by Type ................................................................................................. 14-18
14-11 DEUMR Field Descriptions................................................................................................ 14-20
14-12 DEUKSR Field Descriptions .............................................................................................. 14-21
14-13 DEURCR Field Descriptions .............................................................................................. 14-22
14-14 DEUSR Field Descriptions ................................................................................................. 14-23
14-15 DEUISR Field Descriptions................................................................................................ 14-24
14-16 DEUICR Field Descriptions ............................................................................................... 14-26
14-17 MDEUMR in 'Old' Configuration ..................................................................................... 14-29
14-18 MDEUMR in 'New' Configuration.................................................................................... 14-30
14-19 Mode Register—HMAC or SSL-MAC Generated by Single Descriptor........................... 14-31
14-20 Mode Register—HMAC Generated across a Sequence of Descriptors.............................. 14-32
14-21 MDEURCR Field Descriptions .......................................................................................... 14-33
14-22 MDEUSR Field Descriptions.............................................................................................. 14-34
14-23 MDEUISR Field Descriptions ............................................................................................ 14-35
14-24 MDEUICR Field Descriptions............................................................................................ 14-37
14-25 AESUMR Field Descriptions.............................................................................................. 14-41
14-26 AES Cipher Modes ............................................................................................................. 14-41
14-27 AESURCR Field Descriptions............................................................................................ 14-44
14-28 AESUSR Field Descriptions ............................................................................................... 14-44
14-29 AESUISR Field Descriptions.............................................................................................. 14-46
14-30 AESUICR Field Descriptions ............................................................................................. 14-47
14-31 CCCR Field Descriptions.................................................................................................... 14-55
14-32 CCPSR Field Descriptions.................................................................................................. 14-57
14-33 G_STATE and S_STATE Field Values................................................................................ 14-59
14-34 CHN_STATE Field Values.................................................................................................. 14-60
14-35 Crypto-Channel Pointer Status Register Error Field Definitions........................................ 14-61
14-36 Crypto-Channel Pointer Status Register PAIR_PTR Field Values...................................... 14-61
14-37 CDPR Field Descriptions.................................................................................................... 14-62
14-38 Fetch FIFO Field Descriptions............................................................................................ 14-63
14-39 Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers ................ 14-70
14-40 MCR Field Descriptions ..................................................................................................... 14-74
15-1 eTSECn Network Interface Signal Properties ...................................................................... 15-6
15-2 eTSEC Signals—Detailed Signal Descriptions .................................................................... 15-8
15-3 Module Memory Map Summary......................................................................................... 15-11
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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