Duart Features - Freescale Semiconductor MPC8313E Family Reference Manual

DUART
Data
Address Bus
Control
int
18.1.1

DUART Features

The DUART includes these features:
• Full-duplex operation
• Programming model compatible with the original PC16450 UART and the PC16550D (an
improved version of the PC16450 that also operates in FIFO mode)
• PC16450 register reset values
• FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
• Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
• Maskable transmit, receive, line status, and MODEM status interrupts
• Software-programmable baud generators that divide the system clock by 1 to (2
a 16x clock for the transmitter and receiver engines
• Clear-to-send (CTS) and ready-to-send (RTS) MODEM control functions
• Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
• Line and MODEM status registers
• Line-break detection and generation
• Internal diagnostic support, local loopback, and break functions
• Prioritized interrupt reporting
• Overrun, parity, and framing error detection
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
18-2
Control
Logic
Interrupt
Control
HRESET
system _clk
Figure 18-1. UART Block Diagram
Receive Buffer
Transmit Buffer
Input Port
Output Port
16-Bit Counter/
Baud Rate Generator
16
Freescale Semiconductor
SIN
SOUT
CTS
RTS
–1) and generate