Freescale Semiconductor MPC8313E Family Reference Manual page 23

Paragraph
Number
14.7 Power Saving Mode..................................................................................................... 14-75
15.1 Overview........................................................................................................................ 15-1
15.2 Features .......................................................................................................................... 15-2
15.3 Modes of Operation ....................................................................................................... 15-4
15.4 External Signals Description ......................................................................................... 15-6
15.4.1 Detailed Signal Descriptions ..................................................................................... 15-8
15.5 Memory Map/Register Definition ............................................................................... 15-11
15.5.1 Top-Level Module Memory Map ............................................................................ 15-11
15.5.2 Detailed Memory Map............................................................................................. 15-12
15.5.3 Memory-Mapped Register Descriptions.................................................................. 15-22
15.5.3.1 eTSEC General Control and Status Registers...................................................... 15-22
15.5.3.1.1
15.5.3.1.2
15.5.3.1.3
15.5.3.1.4
15.5.3.1.5
15.5.3.1.6
15.5.3.1.7
15.5.3.1.8
15.5.3.1.9
15.5.3.2 eTSEC Transmit Control and Status Registers.................................................... 15-36
15.5.3.2.1
15.5.3.2.2
15.5.3.2.3
15.5.3.2.4
15.5.3.2.5
15.5.3.2.6
15.5.3.2.7
15.5.3.2.8
15.5.3.2.9
15.5.3.2.10
15.5.3.2.11
15.5.3.2.12
15.5.3.3 eTSEC Receive Control and Status Registers ..................................................... 15-49
15.5.3.3.1
15.5.3.3.2
15.5.3.3.3
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Contents
Enhanced Three-Speed Ethernet Controllers
Controller ID Register (TSEC_ID).................................................................. 15-22
Controller ID Register (TSEC_ID2)................................................................ 15-23
Interrupt Event Register (IEVENT) ................................................................ 15-24
Interrupt Mask Register (IMASK) .................................................................. 15-28
Error Disabled Register (EDIS)....................................................................... 15-30
Ethernet Control Register (ECNTRL) ............................................................. 15-31
Pause Time Value Register (PTV) ................................................................... 15-33
DMA Control Register (DMACTRL) ............................................................. 15-34
TBI Physical Address Register (TBIPA) ......................................................... 15-35
Transmit Control Register (TCTRL) ............................................................... 15-36
Transmit Status Register (TSTAT)................................................................... 15-38
Default VLAN Control Word Register (DFVLAN) ........................................ 15-42
Transmit Interrupt Coalescing Register (TXIC).............................................. 15-43
Transmit Queue Control Register (TQUEUE) ................................................ 15-44
TxBD Ring 0-3 Weighting Register (TR03WT)............................................. 15-44
TxBD Ring 4-7 Weighting Register (TR47WT)............................................. 15-45
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 15-46
Transmit Buffer Descriptor Pointers 0-7 (TBPTR0-TBPTR7) ...................... 15-46
Transmit Descriptor Base Address Registers (TBASE0-TBASE7) ............... 15-47
Transmit Time Stamp Identification Register (TMR_TXTS1-2_ID) ............. 15-48
Transmit Time Stamp Register (TMR_TXTS1-2_H/L) ................................. 15-48
Receive Control Register (RCTRL) ................................................................ 15-49
Receive Status Register (RSTAT).................................................................... 15-51
Receive Interrupt Coalescing Register (RXIC) ............................................... 15-53
Title
Chapter 15
Page
Number
xxiii