Freescale Semiconductor MPC8313E Family Reference Manual page 362

e300 Processor Core Overview
Table 7-8. Differences Between e300 and G2_LE Cores (continued)
e300 Core
Data cache queue sharing
icbt instruction
1-1/2-level bus pipelining
PowerPC little-endian not
supported
Data retry mode removed
External control instructions
removed
Reduced pin mode removed Reduced pin mode available Reduced pinout mode and the signal redpinmode will not be
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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G2_LE Core
—
—
1-level bus pipelining
PowerPC little-endian
supported
Data retry mode available
External control instructions
available
The e300 has a new data cache queue sharing extension that
allows the two burst-write queues in the bus unit to be used
interchangeably for cache replacements and snoop pushes. Thus,
the data cache can support two outstanding cache replacements
or two outstanding snoop push operations on the bus at any given
time.
The e300 supports a new instruction cache block touch instruction
that facilitates preloading the instruction cache before locking; the
G2_LE core requires speculatively fetching instructions before
locking the instruction cache.
For the e300, a new transaction can complete an address tenure
when the previous transaction has been granted the data bus; for
the G2_LE, a new transaction must wait until the previous data
tenure has completed before completing its address tenure.
PowerPC little-endian will not be supported in the e300 core,
although true little-endian will be fully supported.
drtry and drtrymode will no longer be supported on the e300 and
future versions.
The eciwx and ecowx instruction pair will not be supported on the
e300 core. These are optional instructions in the PowerPC
architecture.
supported in the e300 core.
Impact
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