Pit External Signal Description; Pit Memory Map/Register Definition - Freescale Semiconductor MPC8313E Family Reference Manual

5.6.4

PIT External Signal Description

This section provides an overview and detailed descriptions of the PIT signals.
There is one distinct external input signal (PIT clock), defined in
Name Port
PIT_CLK PIT_CLK
Table 5-46 describes of the external PIT signal.
Signal I/O
PIT_CLK I This signal is used as the timebase for the periodic interval timer module.
Meaning
5.6.5

PIT Memory Map/Register Definition

The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIT registers are 32-bit wide and reside on 32-bit address boundaries and should only be accessed as
32-bit quantities.
All addresses used in this chapter are offsets from PIT base, as defined in
Table 5-47 shows the PIT memory map.
Offset
0x00 Periodic interval timer control register (PTCNR)
0x04 Periodic interval timer load register (PTLDR)
0x08 Periodic interval timer prescale register (PTPSR)
0x0C Periodic interval timer counter register (PTCTR)
0x10 Periodic interval timer event register (PTEVR)
0x14–0x1F Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-45. PIT Signal Properties
Periodic interval timer.
Table 5-46. PIT External Signal—Detailed Signal Descriptions
State
Timing
Table 5-47. PIT Register Address Map
Register
Table
Function
Description
—
—
Access
R/W
R/W
R/W
R
w1c
—
System Configuration
5-45.
I/O Reset
I N/A
Chapter 3, "Memory Map."
Reset Value
0x0000_0000 5.6.5.1/5-46
0x0000_0000 5.6.5.2/5-46
0x0000_0000 5.6.5.3/5-47
0x0000_0000 5.6.5.4/5-47
0x0000_0000 5.6.5.5/5-48
—
Pull Up
—
Section/
Page
5-45