Generation Of Start; Post-Transfer Software Response - Freescale Semiconductor MPC8313E Family Reference Manual

2. Update I2CnFDR[FDR] and select the required division ratio to obtain the SCLn frequency from
the CSB (platform) clock.
3. Update I2CnADR to define the slave address for this device.
4. Modify I2CnCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
disable.
5. Set the I2CnCR[MEN] to enable the I
17.5.3

Generation of START

After initialization, the following sequence can be used to generate START:
1. If the device is connected to a multimaster I
(I2CnSR[MBB] = 0) before switching to master mode.
2. Select master mode (set I2CnCR[MSTA]) to transmit serial data and select transmit mode (set
I2CnCR[MTX]) for the address cycle.
3. Write the slave address being called into I2CnDR. The data written to I2CnDR[0–6] comprises the
slave calling address. I2CnCR[MTX] indicates the direction of transfer (transmit/receive) required
from the slave.
The scenario above assumes that the I
2
an I C interrupt is generated (provided interrupt reporting is enabled with I2CnCR[MIEN] =1).
17.5.4

Post-Transfer Software Response

Transmission or reception of a byte automatically sets the data transferring bit (I2CnSR[MCF]), which
indicates that one byte has been transferred. The I
interrupt is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CnCR[MIEN] is set). In the interrupt handler, software must take the following steps:
1. Clear I2CnSR[MIF]
2. Read the I2CnDR in receive mode or write to I2CnDR in transmit mode. Note that this causes
I2CnSR[MCF] to be cleared, as shown in
3. When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If
master receive mode is required, I2CnCR[MTX] must be toggled at this stage (see
If the interrupt function is disabled, software can service the I2CnDR in the main program by monitoring
I2CnSR[MIF]. In this case, I2CnSR[MIF] must be polled rather than I2CnSR[MCF] because MCF
behaves differently when arbitration is lost. Note that interrupt or other bus conditions may be detected
2
before the I C signals have time to settle. Thus, when polling I2CnSR[MIF] (or any other I2CnSR bits),
software delays may be needed to give the I
During slave-mode address cycles (I2CnSR[MAAS] is set), I2CnSR[SRW] should be read to determine
the direction of the subsequent transfer and I2CnCR[MTX] should be programmed accordingly. For
slave-mode data cycles (MAAS is cleared), I2CnSR[SRW] is not valid and I2CnCR[MTX] must be read
to determine the direction of the current transfer (see
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
C interface.
2
C system, check whether the serial bus is free
2
C interrupt bit (I2CnSR[MIF]) is cleared. If MIF is set at any time,
2
C interrupt bit (I2CnSR[MIF]) is also set and an
Figure 17-11.
2
C signals sufficient time to settle.
Figure 17-11).
2
I C Interfaces
Figure 17-11).
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