Freescale Semiconductor MPC8313E Family Reference Manual page 503

LCLK
TA
LAD
LALE
A
LCS n
LWE
LBCTL
Notes:
t
WC
t
AWCS
t
AWE
Table 10-33 lists the signal timing parameters for a GPCM write access as the option register attributes are
varied.
Option Register Attributes
TRLX XACS ACS
0 0 00
0 0 10
0 0 11
0 1 00
0 1 10
0 1 11
0 0 00
0 0 10
0 0 11
0 1 00
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Address
t
AWCS
t
AWE
= Write cycle time.
= Address valid to write chip-select time.
= Address valid to write enable time.
Figure 10-35. GPCM General Write Timing Parameters
Table 10-33. GPCM Write Control Signal Timing
CSNT t
AWCS
0 0
0 ¼
(½)
0 ½
0 0
0 1
0 2
1 0
1 ¼
(½)
1 ½
1 0
t
WC
Write Data
t
CSWP
Latched Address
t
WEN
t = Write chip-select assertion period.
CSWP
t = Write enable negated time wrt chip-selec
WEN
Signal Timing (LCLK clock cycles)
t t
CSWP AWE
2 + SCY 1
1¾ + SCY 1
(2+SCY)
1½ + SCY 1
2 + SCY 1
1 + SCY 1
1 + SCY 2
2 + SCY 1
1½ + SCY 1
1¼ + SCY 1
(1+SCY)
2 + SCY 1
Enhanced Local Bus Controller
1
t t
WEN WC
0 2 + SCY
0 2 + SCY
0 2 + SCY
0 2 + SCY
0 2 + SCY
0 3 + SCY
¼ 2 + SCY
(0)
0 1¾ + SCY
(1½+SCY)
0 1¾ + SCY
(1½+SCY)
¼ 2 + SCY
(0)
10-49