Inbound Message Interrupt Mask Register (Imimr) - Freescale Semiconductor MPC8313E Family Reference Manual

DMA/Messaging Unit
Table 12-8 describes the IMISR register.
Bits Name
31–5 — Reserved
4 MCI Machine check interrupt. Indicates whether a machine check interrupt condition was generated by setting the
IDR[31]. The interrupt is cleared by writing a 1 to IDR[IMC] from the CSB.
0 No machine check interrupt
1 There is a machine check interrupt
3 IDI Inbound doorbell interrupt. Indicates whether an inbound doorbell interrupt occurred.
0 No inbound doorbell interrupt
1 There is an inbound doorbell interrupt
2 — Reserved
1 IM1I Inbound message 1 interrupt. Indicates whether an inbound message 1 interrupt occurred. Write 1 to this
position to clear this bit.
0 No inbound message 1 interrupt.
1 There is an inbound message 1 interrupt.
0 IM0I Inbound message 0 interrupt. Indicates whether an inbound message 0 interrupt occurred. Write 1 to this
position to clear this bit.
0 No inbound message 0 interrupt.
1 There is an inbound message 0 interrupt.
12.3.7

Inbound Message Interrupt Mask Register (IMIMR)

This register contains the interrupt mask of the doorbell and message register events generated by the PCI
master. Figure 12-9 shows the IMIMR fields.
Offset 0x084
31
R
W
Reset
Figure 12-9. Inbound Message Interrupt Mask Register (IMIMR)
Table 12-9 describes the IMISR register.
Bits Name
31–5 — Reserved
4 MCIM Machine check interrupt mask.
0 Machine check interrupt from the IDR is allowed
1 Machine check interrupt is masked. IMISR[MC1] is cleared
3 IDIM Inbound doorbell interrupt mask.
0 Inbound doorbell interrupt is allowed
1 Inbound doorbell interrupt is masked. IMISR[IDI] is cleared.
2 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
12-8
Table 12-8. IMISR Field Descriptions
Descriptions
—
All zeros
Table 12-9. IMIMR Field Descriptions
Description
Access: Read/Write
4 3 2 1 0
MCIM IDIM — IM1IM
Freescale Semiconductor