General Purpose Filer Rule; Time-Stamp Insertion On Transmit Packets - Freescale Semiconductor MPC8313E Family Reference Manual

A representation of the PTP packet is shown in
Preamble
15.6.6.4.1

General Purpose Filer Rule

The eTSEC receive filer has been enhanced with the addition of a general-purpose event bit. This event
bit can be used in conjunction with filing table rules to identify 1588 packets and indicate these packets by
setting special timer status register bits (TMR_STAT). Additionally, 1588 packets can be easily identified
by upper-layer software by using the filer to queue all PTP packets to one or more predefined virtual
queues. See Section 15.6.4.2.1, "Filing Rules
15.6.6.5

Time-Stamp Insertion on Transmit Packets

Software has the option to write the time stamp of the transmitted frame to memory in the padding
alignment bytes (PAL) located between the TxFCB and the frame data. It is required that a minimum of
two TxBDs are used. The first points to the start of the 8 byte TxFCB. The second points to the start of
frame data. In memory, the TxFCB, and at least the first 16 bytes of the TxPAL must be adjacent, that is,
located in continguous memory locations, as depicted in
The first TxBD[TOE] bit is set. When the TMR_CTRL[Record Time-stamp In PAL Enable] and
TxFCB[PTP] bits are set, the timestamp is written to memory location TxBD[Data Buffer Pointer]+16.
The second TxBD's Data Length must either contain the full frame length, or a value greater than the
TxThreshold setting. Refer to
TMR_TXTSn_H/L and TMR_TXTSn_ID registers still function normally.
15.6.6.5.1 Interrupts
The TxPAL is updated with a time-stamp before closing the second TxBD. The TxBD[I] bit can be set for
the second TxBD frame to cause an interrupt (via IEVENT[TXF]) after the time-stamp has been written
to the TxPAL.
When time-stamps are inserted into the TxPAL, the TMR_TXTSn_H/L and TMR_TXTSn_ID registers
still function normally. Therefore, the 1588 interrupt can be triggered by using the TMR_PEVENT register
bits TXP1, and TXP2.
Table 15-160. Time-Stamp Insertion Programming Requirements
Requirement
TMR_CTRL[RTPE]=1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
SFD SRC DEST
10101011
Time Stamp Point
Figure 15-144. PTP Packet Format
for further information.
Table 15-160. When time-stamps are inserted into the TxPAL, the
If TMR_CTRL[RTPE]=0, then no time-stamp is written to a TxPAL.
Figure 15-144.
L/T
IP_H UDP_H
Figure 15-145.
Behavior if requirement is not met
Enhanced Three-Speed Ethernet Controllers
Data CRC
PTP_Message
15-183