Jitter Diagnostics Register (Jd) - Freescale Semiconductor MPC8313E Family Reference Manual

15.5.4.3.9

Jitter Diagnostics Register (JD)

Annex 36A in IEEE 802.3z describes several jitter test patterns. These can be configured to be sent by
writing the jitter diagnostics register. See the register description for more information. In may be wise to
auto-negotiate and advertise a remote fault signaling of offline prior to beginning the test patterns.
Figure 15-127 describes the definition for the JD register.
Offset 0x10
0
R Jitter
Enable
W
Reset
Table 15-135 describes the fields of the JD register.
Bits Name
0 Jitter Enable Jitter enable. This bit is cleared by default.
0 Normal transmit operation.
1 Enable the TBI to transmit the jitter test patterns defined in IEEE 802.3z 36A.
1–3 Jitter Select Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the
following table. Default is 00.
User defined uses custom jitter pattern, bits 6–15
High frequency (+/- D21.5)
1010101010101010101010101010101010101010...
Mixed frequency (+/- K28.5)
1111101011000001010011111010110000010100...
Low frequency
1111100000111110000011111000001111100000...
Complex pattern (10'h17c,10'h0c9,10'h0e5,10'h2a3, 10'h17c,...)
Square Wave (- K28.7)
0011111000001111100000111110000011111000...
Reserved
Reserved
4–5 — Reserved
6–15 Custom Jitter Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired
Pattern custom pattern which is continuously transmitted. Its default is 0x000.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
1 3 4
Jitter Select —
Figure 15-127. Jitter Diagnostics Register Definition
Table 15-135. JD Field Descriptions
Jitter Pattern Select
5 6
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
Custom Jitter Pattern
bit[1] bit[2]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
15
bit[3]
0
1
0
1
0
1
0
1
15-133