Isochronous Endpoint Bus Response Matrix; Managing Queue Heads - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
must write the prime bit. The USB_DR will prime the isochronous endpoint in (micro)frame N – 1 so that
the device controller will execute delivery during (micro)frame N.
Priming an endpoint towards the end of (micro)frame N – 1 will not
guarantee delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N + 1 if device controller does not have enough time to
complete the prime before the SOF for packet N is received.
16.8.3.6.2

Isochronous Endpoint Bus Response Matrix

Table 16-90 shows the isochronous endpoint bus response matrix.
Setup
In
Out
Ping
Invalid
1
Zero Length Packet.
2
Force Bit Stuff Error.
16.8.4

Managing Queue Heads

Figure 16-64 shows the endpoint queue head diagram.
ENDPOINTLISTADDR
Up to
6 Elements
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-146
Table 16-90. Isochronous Endpoint Bus Response Matrix
Stall Not Primed
STALL STALL
1
NULL Packet NULL Packet
Ignore Ignore
Ignore Ignore
Ignore Ignore
Endpoint Queue Heads
Endpoint QH 0—Out
Endpoint QH 0—In
Endpoint QH 1—Out
•
•
•
Figure 16-64. Endpoint Queue Head Diagram
CAUTION
Primed Underflow
STALL
Transmit BS Error
Receive
Ignore Ignore
Ignore Ignore
Transfer Buffer Pointer
Transfer Buffer Pointer
Transfer
Buffer
Pointer
Endpoint Transfer Descriptor
Overflow
N/A N/A
2
N/A
N/A Drop Packet
Ignore
Ignore
Transfer
Buffer
Transfer
Buffer
Transfer Buffer Pointer
Transfer Transfer
Buffer Buffer
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