Output Signal States During System Reset - Freescale Semiconductor MPC8313E Family Reference Manual

Signal Descriptions
Dedicated pin
Dedicated pin
3.3 Output Signal States During Reset
When a system reset is recognized (PORESET or HRESET are asserted), the device aborts all current
internal and external transactions and releases all bidirectional I/O signals to a high-impedance state. See
Chapter 4, "Reset, Clocking, and Initialization,"
During reset, the device ignores most input signals (except for the reset configuration signals) and drives
most of the output-only signals to an inactive state.
Interface
MDM[0:3]
MBA[0:2]
MA[14:0]
MWE
MRAS
MCAS
MCS[0:1]
MCKE
MCK
MCK
MODT[0:1]
PCI_INTA
PCI_RESET_OUT
PCI_GNT[0:2]
UART_SOUT[0:1]
UART_RTS[0:1]
TSEC1_GTX_CLK
1
TSEC1_TXD[3:0]
TSEC1_TX_EN
TSEC2_GTX_CLK
TSEC2_TXD[3:0]
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
3-30
Table 3-3. Reset Configuration Signals (continued)
Functional
Functional Signal Name
Interface
None (dedicated pin)
None (dedicated pin)
Table 3-4. Output Signal States During System Reset
Signal
DDR data mask
DDR bank select
DDR address
DDR write enable
DDR row address strobe
DDR column address strobe
DDR chip select (2/DIMM)
DDR clock enable
DDR differential clocks
DDR differential clocks
DRAM on-die termination
PCI interrupt output
PCI reset output
PCI grant 0–2
DUART serial data out
DUART ready to send
eTSEC1 transmit clock out
eTSEC1 transmit data 2–0
eTSEC1 transmit enable
eTSEC2 transmit clock out
eTSEC2 transmit data 6-4
Reset Configuration Name
CFG_CLKIN_DIV
CFG_LBIU_MUX_EN
for a complete description of the reset functionality.
Table 3-4 shows the states of the output-only signals.
State During Reset
All 'Z'
All 'Z'
All 'Z'
'Z'
'Z
'Z'
Both 'Z'
'0'
'0'
'1'
Both '0'
'Z'
'0'
All 'Z'
All 'Z'
All 'Z'
'0'
All 'Z'
'0'
'Z'
All 'Z'
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