Lblawbar0-Lblawbar3 Bit Settings; Lbc Local Access Window N Base Address Registers; Lblawbar0[Base_Addr] Reset Value - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
5.2.4.3

LBC Local Access Window n Base Address Registers

(LBLAWBAR0–LBLAWBAR3)
The LBC local access window n base address registers (LBLAWBAR0–LBLAWBAR3) are shown in
Figure 5-4.
Offset 0x20, 0x28, 0x30, 0x38
0
R
W
Reset
1. The LBLAWBAR0[BASE_ADDR] reset value depends on the reset configuration word high values. See

"LBLAWBAR0[BASE_ADDR] Reset Value,"

Figure 5-4. LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3)
Table 5-7 defines the bit fields of LBLAWBAR0–LBLAWBAR3.
'
Bits Name
0–19 BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n . The specified
base address should be aligned to the window size, as defined by LBLAWARn[SIZE].
20–31 — Reserved. Write has no effect, read returns 0.
5.2.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value
The core may also use a local bus peripheral device to fetch its boot vector. For this purpose, the
LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word
high BMS field.
Table 5-8 defines the reset value of LBLAWBAR0[BASE_ADDR].
'
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-8
BASE_ADDR
for a detailed description.
Table 5-7. LBLAWBAR0–LBLAWBAR3 Bit Settings
Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS]
0
1
19 20
All zeros
Description
BASE_ADDR Reset Value
0x00000
0xFF800
Access: Read/Write
31
—
Section 5.2.4.3.1,
Freescale Semiconductor