Freescale Semiconductor MPC8313E Family Reference Manual page 33

Paragraph
Number
16.8.3.5.1
16.8.3.5.2
16.8.3.5.3
16.8.3.5.4
16.8.3.6 Isochronous Endpoint Operational Model......................................................... 16-144
16.8.3.6.1
16.8.3.6.2
16.8.4 Managing Queue Heads......................................................................................... 16-146
16.8.4.1 Queue Head Initialization .................................................................................. 16-147
16.8.4.2 Operational Model for Setup Transfers ............................................................. 16-147
16.8.5 Managing Transfers with Transfer Descriptors ..................................................... 16-148
16.8.5.1 Software Link Pointers ...................................................................................... 16-148
16.8.5.2 Building a Transfer Descriptor .......................................................................... 16-148
16.8.5.3 Executing a Transfer Descriptor ........................................................................ 16-149
16.8.5.4 Transfer Completion .......................................................................................... 16-150
16.8.5.5 Flushing/Depriming an Endpoint ...................................................................... 16-150
16.8.5.6 Device Error Matrix........................................................................................... 16-151
16.8.6 Servicing Interrupts................................................................................................ 16-151
16.8.6.1 High-Frequency Interrupts................................................................................. 16-151
16.8.6.2 Low-Frequency Interrupts ................................................................................. 16-152
16.8.6.3 Error Interrupts .................................................................................................. 16-152
16.9 Deviations from the EHCI Specifications ................................................................. 16-152
16.9.1 Embedded Transaction Translator Function .......................................................... 16-153
16.9.1.1 Capability Registers........................................................................................... 16-153
16.9.1.2 Operational Registers......................................................................................... 16-153
16.9.1.3 Discovery........................................................................................................... 16-153
16.9.1.4 Data Structures................................................................................................... 16-154
16.9.1.5 Operational Model ............................................................................................. 16-154
16.9.1.5.1
16.9.1.5.2
16.9.1.5.3
16.9.1.5.4
16.9.1.5.5
16.9.2 Device Operation ................................................................................................... 16-156
16.9.3 Non-Zero Fields the Register File ......................................................................... 16-157
16.9.4 SOF Interrupt ......................................................................................................... 16-157
16.9.5 Embedded Design .................................................................................................. 16-157
16.9.5.1 Frame Adjust Register ....................................................................................... 16-157
16.9.6 Miscellaneous Variations from EHCI .................................................................... 16-157
16.9.6.1 Discovery........................................................................................................... 16-157
16.9.6.1.1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Contents
Setup Phase.................................................................................................... 16-142
Data Phase ..................................................................................................... 16-142
Status Phase ................................................................................................... 16-143
Control Endpoint Bus Response Matrix ........................................................ 16-143
Isochronous Pipe Synchronization ................................................................ 16-145
Isochronous Endpoint Bus Response Matrix................................................. 16-146
Microframe Pipeline ...................................................................................... 16-155
Split State Machines ...................................................................................... 16-155
Asynchronous Transaction Scheduling and Buffer Management ................. 16-156
Periodic Transaction Scheduling and Buffer Management ........................... 16-156
Multiple Transaction Translators................................................................... 16-156
Port Reset....................................................................................................... 16-157
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