An Expansion Register (Anex); An Next Page Transmit Register (Annpt) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Bits Name
10 Full Full-duplex capability. This bit is read-only.
Duplex 0 Link partner is not capable of full-duplex mode.
1 Link partner is capable of full-duplex mode.
11–15 — Reserved, should be cleared.
15.5.4.3.5

AN Expansion Register (ANEX)

Figure 15-123 describes the definition for the ANEX register.
Offset 0x06
0
R
W
Reset
Table 15-131 describes the fields of the ANEX register.
Bits Name
0–12 — Reserved, should be cleared.
13 NP Next page able. This bit is read-only and returns 1 on read. While read as set, indicates local device supports
Able next page function.
14 Page Page received. This bit is read-only. The bit clears on a read to the register.
Rx'd 0 Normal operation.
1 A new page was received and stored in the applicable AN link partner ability or AN next page register. This
bit latches high in order for software to detect while polling.
15 — Reserved, should be cleared.
15.5.4.3.6

AN Next Page Transmit Register (ANNPT)

Figure 15-124 describes the definition for the ANNPT register.
Offset 0x07
0 1
R Next
Msg
—
Page Page
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-130
Table 15-130. ANLPBPA Field Descriptions (continued)
—
Figure 15-123. AN Expansion Register Definition
Table 15-131. ANEX Field Descriptions
2 3 4 5
Toggle
Ack2
Figure 15-124. AN Next Page Transmit Register Definition
Description
All zeros
Description
Message/Un-formatted Code Field
All zeros
Access: Read only
12 13 14
NP Able Page Rx'd
Access: Mixed
Freescale Semiconductor
15
—
15