Freescale Semiconductor MPC8313E Family Reference Manual page 536

Enhanced Local Bus Controller
Bits Name
10–11 G0H General purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases 3 and 4
(second half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
12 G1T1 General purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases 1
and 2 (first half phase).
13 G1T3 General purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases 3
and 4 (second half phase)
14 G2T1 General purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter phases 1 and
2 (first half phase).
15 G2T3 General purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter phases 3
and 4 (second half phase).
16 G3T1 General purpose line 3 timing 1. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases 1
and 2 (first half phase).
17 G3T3 General purpose line 3 timing 3. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases 3
and 4 (second half phase).
G4T1/DLT3 General purpose line 4 timing 1/delay time 3. The function of this bit is determined by M x MR[GPL4].
18
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T1/DLT3 defines the
state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), if a read burst or single
read is executed, G4T1/DLT3 defines the sampling of the data bus as follows:
0 In the current word, the data bus should be sampled at the start of bus clock quarter phase 1 of the
next bus clock cycle.
1 In the current word, the data bus should be sampled at the start of bus clock quarter phase 3 of the
current bus clock cycle.
G4T3/WAEN General purpose line 4 timing 3/wait enable. Bit function is determined by M x MR[GPL4].
19
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T3/WAEN defines the
state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), G4T3/WAEN is used to
enable the wait mechanism:
0 LUPWAIT detection is disabled.
1 LUPWAIT is enabled. If LUPWAIT is detected as being asserted, a freeze in the external signals
logical values occurs until LUPWAIT is detected as being negated.
20 G5T1 General purpose line 5 timing 1. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 1
and 2 (first half phase).
21 G5T3 General purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 3
and 4 (second half phase).
22–23 REDO Redo current RAM word. Defines the number of times to execute the current RAM word.
00 Once (normal operation)
01 Twice
10 Three times
11 Four times
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-82
Table 10-40. RAM Word Field Descriptions (continued)
Description
Freescale Semiconductor