Loss Of Arbitration And Forcing Of Slave Mode - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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from the slave. When no acknowledge is received (I2CnSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CnCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read
of I2CnDR then releases SCLn so that the master can generate a STOP condition. See
17.5.8.2

Loss of Arbitration and Forcing of Slave Mode

When a master loses arbitration the following conditions all occur:
I2CnSR[MAL] is set
I2CnCR[MSTA] is cleared (changing the master to slave mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Thus, the slave interrupt service routine should first test I2CnSR[MAL] and software should clear it if it
is set. See
Section 17.4.2.1, "Arbitration Control."
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
I
C Interfaces
Figure
17-11.
17-23

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