Freescale Semiconductor MPC8313E Family Reference Manual page 129

Offset
0x2_44C8– Reserved, should be cleared
0x2_44FF
0x2_4500 MACCFG1—MAC configuration register 1
0x2_4504 MACCFG2—MAC configuration register 2
0x2_4508 IPGIFG—Inter-packet gap/inter-frame gap register
0x2_450C HAFDUP—Half-duplex register
0x2_4510 MAXFRM—Maximum frame length register
0x2_4514– Reserved, should be cleared
0x2_451C
0x2_4520 MIIMCFG—MII management configuration register
0x2_4524 MIIMCOM—MII management command register
0x2_4528 MIIMADD—MII management address register
0x2_452C MIIMCON—MII management control register
0x2_4530 MIIMSTAT—MII management status register
0x2_4534 MIIMIND—MII management indicator register
0x2_4538 Reserved, should be cleared
0x2_453C IFSTAT—Interface status register
0x2_4540 MACSTNADDR1—Station address register, part 1
0x2_4544 MACSTNADDR2—Station address register, part 2
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 2-2. Memory Map (continued)
Register
eTSEC1 MAC Registers
Access Reset
— —
R/W, R 0x0000_0000
R/W 0x0000_7000
R/W 0x4060_5060
R/W 0x00A1_F037
R/W 0x0000_0600
— —
R/W 0x0000_0007
R/W 0x0000_0000
R/W 0x0000_0000
W 0x0000_0000
R 0x0000_0000
R 0x0000_0000
— —
Special 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Memory Map
Section/Page
—
15.5.3.4.1/15-64
15.5.3.4.2/15-64
15.5.3.4.3/15-65
15.5.3.5.4/15-71
15.5.3.5.5/15-72
—
15.5.3.5.6/15-72
15.5.3.5.7/15-73
15.5.3.5.8/15-74
15.5.3.5.9/15-75
15.5.3.5.10/15-75
15.5.3.5.11/15-76
—
15.5.3.5.12/15-76
15.5.3.5.13/15-77
15.5.3.5.14/15-78
2-23